Atrenta Introduces Predictive Analysis Solution, Providing Earlier, Better Optimization of Chip Designs

Using advanced static and dynamic analysis, 1Team:Analyze diagnoses structural, coding and consistency problems early in the design cycle, at the register transfer level (RTL). It traces problems to their source, guides users to successful resolutions and can even automatically fix errors. It pinpoints critical problems and sub-optimal design elements normally discovered, if at all, much later, after time-consuming simulation, synthesis and gate-level analysis. Examples include synchronization and SoC integration requirements, combinatorial loops and inefficient resource utilization.

1Team:Analyze also validates that design constraints are correct and consistent throughout the design cycle, and it performs comprehensive and extensible electrical rules checking (ERC). In addition, 1Team:Analyze Test and 1Team:Analyze Power options enable users to tune and automatically correct their RTL designs to meet testability and power consumption goals.

"The traditional IC development paradigm has been to design, debug and do over repeatedly, which is intrinsically inefficient and expensive," said Simon Young, Atrenta's senior business unit director. "With 1Team:Analyze, logic designers can finally get it right the first time, closing RTL early and eliminating a huge amount of iteration and back-end work. In effect, 1Team:Analyze shifts the bulk of the development effort from the later, implementation stages -- where impact is limited and the cost and complexity are highest -- to the front end, where leverage is greatest and the cost and complexity are minimal."

Predicting Outcomes & Automatically Optimizing Design

Applying Atrenta's proprietary Predictive Analysis technology, 1Team:Analyze anticipates the downstream effect of RTL design choices and identifies potential problems and areas in need of optimization. In addition, a unique AutoFix capability can automatically correct key testability and power issues. In detecting problems and helping effect their resolution, 1Team:Analyze leverages decades of accumulated design experience. It integrates a large base of industry-standard best practices, as well Atrenta's own extensive experience working with industry-leading customers. It includes design reuse compliance checks such as STARC and OpenMORE to enforce consistent style throughout the design, ease the integration of multi-team and multi-vendor IP and promote design reuse.

The predictability and precision made possible by 1Team:Analyze are especially critical as chip processes shrink to 130nm and below. 1Team:Analyze has the run-time performance, precision and accuracy to quickly process the most complex, multimillion-gate designs in their entirety.

1Team:Analyze also automatically verifies that design constraint files are valid and consistent across all phases of development and all levels of the design hierarchy. Moreover, 1Team:Analyze includes a comprehensive, extensible and implementation tool-independent ERC capability to quickly catch any errors introduced through designer oversight or by design tool bugs.

Test and Power options

In addition to these standard features, 1Team:Analyze offers two powerful optional capabilities. The 1Team:Analyze Test option predicts ATPG (automatic test pattern generation) test coverage and pinpoints testability issues as the RTL description is developed. Users can build testability into their logic designs, apply robust design-for-test (DFT) methodologies and maximize test coverage without becoming test experts themselves. The 1Team:Analyze Power option enables users to tune their RTL designs for power consumption, eliminating much of the back-end work traditionally required.

Seamless Integration Into Existing Flows

1Team:Analyze is fully compatible with industry-standard tools and methodologies and blends smoothly into customers' design flows. In effect, 1Team:Analyze upgrades existing development infrastructures and tools to provide a new level of engineering productivity, precision, teamwork and overall product quality.

1Team:Analyze is part of a growing family of Predictive Development solutions from Atrenta. Other members include 1Team:Verify, also unveiled today, and the recently introduced 1Team:Implement suite. 1Team:Verify is the first solution to bring the benefits of sophisticated assertion-based verification (ABV) to logic designers, enabling detection and prevention of hard-to-find bugs at the early stages of design, without any verification expertise. 1Team:Implement enables IC architects, logic designers and implementation teams to optimize physical aspects of their designs, including timing, area and congestion.

About Atrenta

Atrenta Inc. is the leading provider of Predictive Development solutions for companies creating complex chips, systems and embedded software. Predictive Development is a new class of design automation solution that turns the costly and error-prone activity of electronic development into a more predictable, manageable and reliable process. Atrenta's 1Team Family of Predictive Development solutions enhances the entire development cycle -- from architectural planning to physical implementation, and from hardware to embedded software. Atrenta is headquartered in San Jose, Calif., with a research and development center in Noida, India. For further information, visit the Atrenta website at http://www.atrenta.com/, email moreinfo@atrenta.com or call 408-453-3333.

NOTE: Atrenta is registered trademark and ITeam is a trademark of Atrenta Inc. All other trademarks belong to their respective owner.

CONTACT: Jane Evans-Ryan of MCA, +1-650-968-8900, or jryan@mcapr.com,
for Atrenta Inc.; or Mona Singh, Marketing Communications Manager of Atrenta
Inc., +1-408-467-4248, or mona@atrenta.com

Web site: http://www.atrenta.com/